Microprogrammed data processing system utilizing improved storage addressing means

ABSTRACT

A data processing system characterized by a high speed local storage unit used for storage of addresses and data involved in a variety of operations. Accesses to a main storage unit, containing both macroprogram and microprogram information, is under the control of addresses held in local storage. Transfer from a main line program to an interrupt subroutine is also handled by the local storage unit.

United States Patent Humberto Cordero, ,Ir.

Inventors Endlcott;

Edward G. Drimak, Johnson Cit Richard J. Hutchinson, Vestal; Michael F.

Schaughency, Endwell; Everett Shimp,

Endwell, all 0, N.Y.

Jan. 2, 1968 Aug. 10, 1971 1 Y International Business Machines 1Corporation Armonlt, N.Y.

App] No. Filed Patented Assignee \IICROPROGRAMMED DATA PROCESSING SYSTEML'TlLlZlNhlMPROVED STORAGE ADDRESSING'MEANS 1 15 Claims.22 Drawing Figs.

US. Cl 340/1725, 235/157 1m.c|... G06I9/16 FleldotSearch 340 172.5;

1 MAIN STOARAGE 0 TA IASSEIBLER [56] References-Cited I UNITED STATESPATENTS 3,029,414 4/1962 Schrimpf 340/1725 3,247,490 4/1966 Kregness eta 340/1725 3,344,404. 9/1967 Curewitz ,1 340117215 3,359,544 12/1967Maconetal. 340/1725 3,369,221 2/1968 Lethin etal 340 1725 ThreadgoldetalPn'marj/ EXarniner PaUlJ Henon Assistant Examinr- Melvin B. ChapnickAttorneys-Hanifin and Jancin and Carl W. Laumann. Jr.

ABSTRACT: A dataprocessing system characterized by a high speed localstorage unit used for storage of addresses and data involved in avariety of operations. Accesses to a main storage unit, containing bothmacroprogram and microprogram' information, is under the control ofaddresses held in local storage. Transfer'from a mainline program to aninterrupt subroutine is also handled by the local storage unit 4 1140115 A llllSK are LOCAL stun/1G5 I oqncssm PATENTEU AUG 1 01971 SHEET01 0F Q VI F 0E m mm may m mm \H 1 I i a g a i M a j 2 m WOGJEM W |-l WTDLT aiming? ima e m V mm W BA R 25102 2 ng w mmw m gas is m HEmME v W022 E2 p w 1 258 fi $552 magma 522m 4]. wuss: rm i1 w T 555 Lil WEE em M2 $531 m2 is 52 H i E; i 32f H2 2 5: m N K m 522 5 ma W 31E? 55E \3 mATTORNEY PAIENTEI] mm 0 I97! CICY SHEET 02 OF START MICRO- ROUTINE READMACHINE LANGUAGE INSTRUCTION F ROM THE PROGRAM STORAGE AREA CICY MICRO-ROUTINE PLACE THE MACHINE LANGUAGE INSTRUCTION INTO LOCAL STORAGE CIGYMICRO ROUTINE DECOOE THE INSTRUCTION AND DETERMINE WHAT MICROROUTINE TOBRANCH TO FOR EXECUTION.

XXXY

MICRO- ROUTINE OPERATE ON THE CURRENT MACHINE LANGUAGE INSTRUCTION.SEVERAL MICROROUTINES CAN BE ENVOLVEO IN nus OPERATION OPERATIONCOMPLETE PATENTED AUG I 0 1921 3,599,176

SHEET 03 [1F 1 FIG 3 FIG. 30 FIG. 3b FIG. 3c

FIG. 3d H1634: FIG. 3f

C REGISTER OR F;

CREGISTER our OR s m smus LlNES B 21 READ CALL STORAGE CONLROLS I 30501v. usr: AUX. STORAGE' CLOCK 1 17 2 31 5? FILE DATA m BITSMIL A REG. BUSmm 1 STORAGE mm STORAGE DA A STORAGE BREQBUSJ DATA REGISTER L PATENTEUAUEIOTSTI 3,599,176

saw on or 18 A FIG. 3b

1/0 DEVICES TRAP REQUEST EXTERNAL BUS IR C REG.

EXTERNAL BUS OUT CONSOLE C REG LOCAL STORAGE LOCAL STORAGE e REG. BUSDATA ASSEMBLER mm [)0 REG. BIT SAT Z BUS READ LSDBO 8 YLINES 8X LINESPATENTEU AUGIOISTI 3599176 sum as or 18 FIG. 3c

BRANCH CONDITION A REGISTER A REGBUS BRANCH CONDITION A II B REGISTERASSEIIBLER B REGISTER B REC, BUS

B REGISTER MODIFIER PATENTED AUG 1 0 |97| SHEET 05 GE SE AUX STORAGE N0G ASSEN BRANCH CONDITION GONTROl SAT LINES I E 2 I B d T 9 2 w L R R m aE E H B 5 5 M G H G MW 0 0 CL MM LR M i 2 nuluo w 0 MI P D E M m M A T 6R R 6 l. L R T om m a P5 0 Mr... M 1 M AU Du S E 5 M L A A J I! E t g EF I! u 0 l-\ a i 6 In. R 0 E m c R mLS C W0 R ISTER W0 REG. SET

W1 REGISTER w ZER NR] 0 UPDATE E man FIG. 3d

PATENIED Am; I 0 IHTI SHEEL, 07 0F 18 III LDa0 I} n I Inc .AIIo I III,

f w [m M m M A i m i W ZBUS,

! B?" m M 44, [1/0 REG.\[]

91 MODE IIIISK REGISTER REGISTER 92 ANY BIT H GATE OTHRUG M V LIIIEs I Ias LOCAL LOCAL IIIII A15 ADDRESS 124 J ASSEMBLER LL) 3 0mm I I max LINESm I I1I,I19 5/ LOCAL/83 /85 sToR REA'D -RI-IIID WRITE CREGEZ maconz & m80 I INHIBIT LINE f comm LINE}; WES j 84 LOCAL A5 STORAGE i CREGE[)ECQDE ADDEsS ASSEMBLER E8. as d u DECODE -u FIG. 3e

PATENTEUAUGIOIHTI 3.599.176

SHEET 08 0F 18 a i M J f ,100 ,AREG. BUS GREG-E curfr goLs m m L m in. wN BREE GAEES GREG. cp1@ L STRAIGHT CROSS CONTROLS 0 0 i BUS SREG 46 E EW5 CARRY MU E INSERT M A 9 1 L a 1 5 REGISTER W5 \L &

CONTROLS 41a [TRUE an GARRY COMFLEMENT) 9 can CARRY} 1B|T GARRYL I u. myU ,53 mums nm N) coumnon REGISTER 13 CONTROLS PATENTED AUG 1 0 I97ISHEET 09 DF READ LINE WRITE LINE AS FORCED READ AS FORCED WRITE ASNORMAL READ AS NORMAL WRITE BS ODD READ BS ODD WRITE BS EVEN READ BSEVEN WRITE LS ADDRESS LINE RESET LOCAL STORAGE FIG. 4a

PATENTED AUGI 0 I00 LOCAL STORAGE X ADDRESS ASSENRLER SHEET 10 DF 05ADDRESSING READ-WRITE LINES 0E000E AND INHIBITS 85\ THE As FORCEDPROVIDES LINES TO READ AND WRITE LINES, A5 NORMAL READ mow THE READNORMAL AS NORMAL WRITE WRITE LINES TO BE AND WRITE LINES ACTIVE ()R m BS000 READ AND B5000 READ INHIBIT THE WRH'E WRITE LINES AND BS DDD WRITEOPERATION E R Q 0s EVEN READ GATED FOR GIVEN BS commons AT GIVEN T0PROVI READ 0R WRITE OF LOCAL STORAGE AS 0Ec00E UNIT BITS 5,6 ANDTOF THEAS CTRLREG. ARE 0E000E0 AS FOR ADDRESSING AS 8I\ A5 A5 A8 as 0E000E UNITBITS 9104010 OF THE 35 CTRL. REcv ARE 0E000E0 B5 FOR ADDRESSING mmSTORAGE 94 96 ZEN ZES RR :RRR'

LS ZONE BITO LS ZONE DECODEO L5 ZONES ARE GENERATEDFROM LS ZONE 0E000E1ggMBINEDWITH THE MODE REG. LS ZONE mom 4 A BITS 566E AND 1 L5 ZDNEDECDDE 5 Y UNE FOR g g ff LS ZONE 0Ec00Ee ADDRESSING By BIT IN THE LSZONE DECODE 1 L001 5 ONE MMSKREG WHICH ARE SET BY 1/0 TRAPS AS AND 05READ/WRITE LINES Y-LINE CONTROLS YLINE GATES AND GATES CONTROL LINES AREDEGITES GENERATED HERE. BACKUP CONTROL LINES FOR AS BITO BACK UPAREA AREALSO DEVELOPED FIG. 4b

PAIENIEI] 11001 01011 SHEET 11 [1F 18 126 10 1 1101010111111 C1110111111s1100'11H 1E1 1 1250 PH BUFFERED CHNLHIREQ 111101111115120111111011 11111 A mb DISK F mu PH BUFFERED 111130 011111111E0 J 11 1110111111 11 101s110111r111 A 128b- SS ESE Z 120 PH BUFFERED011110 READER 11E0 I 11101111111101101110. AP A 4280 129 PH BUFFERED01110 PUNCH REG 1 11 01110101011111. A 11010 NOTI'NHIBITCARDJLP PH001111110 01111110111110 I 011111 1011 1E1 r- 14 GATE 011111111: 11500151 b A PH BUFFERED 0110111 11E0 131 ,15211 0011111111s11v11E 15111BUFFERED 011111. 0111 REO 111011011101111111'11 A 10 GATE 011111 011001111 11111 r l 001111 1151 11 A 111011011110011111 P A OR1110111111510 1; 1 0R 5 1 1111. KREG. 0011110111111 SRV 011 0 BUFFERED1111011. 01111. 11101111E10E11 SELECT 1110- A 101110. 51111111 22 11101)GATE 011111' 11111 140 SAMPLE 0P0 140 TRAP REQ PH NOT INHIBIT 1/0 RED. LN 1110111011E0 104 101 1 1111011! 1340 PH 1101111110 101 1 1110.1110111111011 REG. 01111. A INOTWIISK M 1050- PH BUFFERED 01s.11EsE111E0.

51011111 11101 011011 OR A 19 1 10110 111011 1 k I MACH CHK LATCH :5613%,, PH EUFFERED M/ICH. CHK. REQ 1110111111511 A 111011111151111E001 am Am PH 0011E11E051011EE111101111E0 0 STORAGEIVIOLATION A 1 010111111110011 1111111 FIG.

PATENTEDAUBIOBYI 3 SHEET 13 HF 18 T FIG. 7

21 MAIN STORAGE ADDRESS ASSEMBLER L j 7 LOCAL H ASSEMBLER LOCAL STORAGE23 ,29 anssu" M0 M1 REGISTER REGISTER 35 as 2s 21 l a ans A B REGISTERREGISTER ASSEMBLER ASSEMBLER I U DYNAMIC 3%2P& PRIORITY CONTROLS 10 ILOCAL r STORAGE 53 ADDRESS 9,1 T l MMSK i REGISTER i I I MW"... 3 1 MMSKWORD DETECTION g I I RETURN STORE GATE "0 T0 LQCAL STORAGE FUNCTIONBACKUP +GATEM1TOAREG. a THRU ALU g FUNCT'ON GATEALUTO LOCAL STORAGEGI\TE LOCAL STORAGE T0 N0 PATENTED mm 0 11111 FIRST READ CYCLE SECONDREAD CYCLE RES/ll 7/176 5 7191/67 (ff/F FIRST WRITE CYCLE SECOND WRITECYCLE SHEU 18 [1F 18 FILE SHARE CYCLES READ 11 1 s c AS0 URGE I11-501111015 110 111 o'12's4se;11191o;11121s 1415 510111: E 11 5 115101111111 Y 1 s 11 1111111 $101115 IE- 11111111 1 +1 :5 1-151; o 1 1 10 o o 1 1 o 1 1 1 o o 0 mm 11/ 7//[ 11m 001/1110 0 FIG.1 u

w 1 s c 1-50111101 150111105 111 111 01234561789i0i1112151415 EB #11 1 101mm 1 s 511111 15 1 1115s -1 v 011110001100'01010 01050 19/ 55001 051/1111; arm/1r m m H G 10b WRITE 111 1 s c 1-50111101 11sou11c1-: 110111 0121456111191011112111115 1 111111 s111111s :1 1111111 +1 :s 1-1111:1 o 1 11 1 o o o 1 1 o 1 1 1 o o 0 mm arr/151mm comm/0 FIG 10c 11 1 s c11-50111101: B-SOURCE 11c 11 o12115s;1as1o:11121s1115 1B "1 1 cou111 s$1011 1s :1 1-1111; 1 -1 1 1 .s 11 1 o 1 o o o 1 1 11 0 0 1 o 1 o FIG.10d

MICROPROGRAMMED DATA PROCESSING SYSTEM UTILIZINGIMPROVEDSTORAGEAERJSSING MEANS BACKGROUND OF THE INVENTION 1. Field ofthe Invention This invention relates generally to electronic dataprocessing systems and, more particularly, to such systems operatingaccording to microprogramming techniques or utilizing a high speed localstorage unit for the maintenance of addresses and data.

2. Description of the Prior Art Microprogramming techniques have beenknown and utilized for the control of data processing systems for sometime. The following literature references are illustrative:

a. M. V. Wilkes, The Best Way to Design an Automatic CalculatingMachine, Manchester University Computer Inaugural Conference,Manchester, England, July 1951.

b. M. V. Wilkes, J. B. Stringer, Microprogramming and the Design ofControl Circuits in an Electronic Digital Computer, Proceedings,Cambridge Philosophical Society, Vol. 49, pt. 2, Apr. 1953.

c. M. V. Wilkes, Microprograrnming, Proceedings East em Joint ComputerConference, 1958.

d. E. M. Grabbe, S. Ramo, D. E. Wooldridge, (eds.), Handbook ofAutomation Computation and Control, Vol. 2, John Wiley, 1959.

c. J. T. Gilmore, Jr., H. P. Peterson "A Fundamental Description of theTX-O Computer, Memorandum 6M-4789b, Lincoln Laboratories, M. I. T., Oct.3, I95 8.

f. M. V. Wilkes, W. Renwick, D. J. Wheeler, The Design of the ControlUnit of an Electronic Digital 'Computer," Proceedings IEE Vol. [05, pt.B, Mar. I958.

The tendency has been to store the microprogram information in aread-nly storage unit. There are a number of reasons for this. First, itavoids the problem of addressing two kinds of information in a singlestorage unit. Second, it prevents the in advertent destruction ofcontrol information which is absolutely essential to the systemoperation. The use of read-only store is not without disadvantages. Themost significant disadvantages are the relatively higher cost and theinflexibility which accompany its use.

Some of the disadvantages can be overcome by the use of separatewritable storage units for program and control information. Thissolution is only partially effective from the cost standpoint. Thefullest advantage can be obtained by the use of a single storage unit tocontain both program and control information. This approach has beenlargely ignored due to the difficulty of handling the addressing,together with the fact that control and program information cannot besimultaneously obtained from storage.

Accordingly, it is a general object of this invention to provide animproved data processing system.

A particular object of the invention is to provide an improvedmicroprogrammed data processing system.

Another particular object of the invention is to provide an improvedlocal storage unit for a data processing system.

A specific object of the invention is to provide an improved means fortransferring data to or from a data processing system where the formatof the data being transferred must be altered or monitored during thetransfer.

Another specific object of the invention is to provide an improved meansfor performing input/output (I/O) operations in a data processingsystem.

Still another specific object of the invention is to provide an improvedmeans for addressing a local storage unit.

A further specific object of the invention is to provide an improvedmeans for handling interrupt requests.

Yet another specific object of the invention is to provide an improvedlocal storage unit for handling interrupt routines.

SUMMARY OF THE INVENTION In accordance with one aspect of the invention,data may be transferred between an [/0 device, such as a disk file, andcore storage within the central processing unit while preserving thearbitrary division of storage by word marks or group mark word marks orany other arbitrary set of selected characters.

A microroutine loop two instructions long causes the central processingunit (CPU) to fetch a character from core storage. This character isinvestigated to determine whether or not it is a special character.Depending on the mode of the transfer, the special characters may bestripped, modified or left unchanged. Further, control action, such asterminating the transfer, may be taken when a special character isrecognized. Since the fetching from the addressed location in corestorage is performed before the data from an external device isavailable, there is essentially no delay caused by the comparison of thecharacter being investigated with the special character to determinewhether or not a match exists.

The second microinstruction merely branches back to the first. While thefirst microinstruction includes a bit pattern which is effective toincrement the data address in main storage, this portion is inhibiteduntil the data transfer is complete. The two instruction loop merelycontinues to loop until the data transfer is complete, at which pointthe data address is incremented to fetch the next character.

A second aspect of the invention relates to the manner in which theactual data transfer between the CPU and 1/0 devices is effected. In thecase of microprogrammed systems, [/0 operations are usually performed onan interrupt basis by a series of microinstructions which set up thevarious gates and addressing circuits to effect the transfer.

While this approach is satisfactory in some cases, it has thedisadvantage of requiring an undue amount of time simply for reading themicroinstructions from storage. There is a further problem presented bythe microprogram approach in that this usually requires a certain amountof housekeeping" to prevent the loss 'of information contained inregisters which are used in the interrupt routine.

In this invention, the selected interrupt signal is effective to forcean arbitrary bit pattern into the control register. This bit pattern issimilar to that which would be placed in the control register by aninterrupt routine used for the same purpose. However, the pattern isforced without an access to main storage for control information.Further, no time is lost in preserving registers which are not used inthe routine.

The usual I/O operation will require more than one load into the controlregister. The subsequent bit patterns are forced by a series of latcheswhich are actuated in sequence.

The result is a system which can accommodate [/0 operations at virtuallyany point in a program without concern for the storage of registers orthe consumption of an undue amount of time.

Another aspect of the invention provides a novel means for developingaddresses in a local storage unit. In the described embodiment, thelocal storage unit contains 64 bytes of information. The 64 bytes aregrouped into six zones. One zone has 16 bytes and the other five have 8bytes each. The remaining 8 bytes are addressable with any one of fourofthe 8-byte zones.

While the exact function of local storage will subsequently be describedin greater detail, it is sufficient to consider it as a temporaryrepository for data, main storage addresses, counters and indicators.

Each zone contains the information relating to a particular class ofoperation. For example, one zone of 16 bytes is used for the CPU classor mode of operation. An 8-byte zone is used in the card reader-punchmode. A further 8-byte zone is used in the mode which is operativeduring data transfers involving a disk file.

In geometric terms, the zone may be considered as the Y address whilethe particular byte within the zone is the X address. The X addressesare selected according to the content of the control register. Certainbit positions of the microin-

1. In a data processing system having a logical configuration determinedlargely by the control word contained in a control register, mainstorage means containing a plurality of control words sequentiallyarranged according to the operations to be performed, a storage addressregister connected to said main storage means for specifying theaccessed location, modifier means connected to said storage addressregister for incrementing an address in said storage address register,means for developing a cycle steal request signal, means responsive tosaid cycle steal request signal for inhibiting the operation of saidmodifier means, and means connecting said means responsive to said cyclesteal request signal to said control register means, said meansresponsive to said cycle steal request signal being further responsiveto said request signal to successively force at least two differentcontrol words into said control register.
 2. The combination accordingto claim 1 further including, buffer means connected to said modifiermeans for storing an address incremented by said modifier means=, andmeans for transferring the modified address from said buffer means tosaid storage address register.
 3. The combination according to claim 1wherein said means for developing a cycle steal request signal isconnected to an input-output device to develop said signal in responseto a demand for service.
 4. The combination according to claim 1including means for connecting said means for developing a cycle stealrequest signal to an input/output device, said means for developing acycle steal request signal developing said signal in response to ademand for service from said device.
 5. In a data processing systemhaving a main storage unit and a control word register, a local storageunit having a plurality of addressable zones, each zone containing aplurality of addressable words representing storage addresses in saidmain storage units, local storage address assembler means for generatingword and zone addresses for said local storage unit, a mode registerconnected to said address assembler means for specifying the zoneaddress, said mode register containing data indicating the type ofoperation of said system, and gating means directly connecting saidcontrol word register to said local storage address assembler means forspecifying the word address.
 6. The combination according to claim 5wherein each zone of said local storage unit contains the main storageaddress of an instruction in a sequence related to the system operationswhich utilize the zone.
 7. The combination according to claim 5 furtherincluding, an address modifier for said main storage unit, said modifieroperating to increment the main storage unit address to address the nextsucceeding location, branch detecting means responsive to the output ofsaid control register means for developing a signal indicating thebeginning or end of a branch routine, means connected to said localstorage address assembler means and responsive to said branch detectingmeans for developing a predetermined word address in local storage, andmeans responsive to said control register means and said local storageaddress assembler means for storing said incremented main storage unitaddress at said predetermined word address in said local storage unit.8. The combination according to claim 7 wherein said predetermined localstorage word address is the same for a plurality of zones.
 9. Thecombination according to claim 5 further including, a MMSK register forspecifying the zone address, means responsive to said control registerfor entering data into said MMSK register, and trap control meansresponsive to said MMSK register for degating said mode register fromsaid address assembler means anD substituting said MMSK registertherefor.
 10. The combination according to claim 9 wherein the dataentered into said MMSK register by said means responsive to said controlregister is fetched from said main storage unit.
 11. The combinationaccording to claim 9 wherein said means for entering data into said MMSKregister comprises, means for monitoring trap requests, addressgenerating means responsive to said monitoring means for developing amain storage address representing an active trap request, and means forfetching the data from said main storage address and entering a portionthereof into said MMSK register.
 12. The combination according to claim11 wherein said address generating means is operative to generate mainstorage addresses awarding priority to the most significant ofcontending requests by generating the highest value address in responseto the highest priority request, whereby the significance of lowerpriority lower value addresses is eliminated through redundancy.
 13. Ina microprogrammed data processing system having a central processingunit, a storage unit and at least one input/output device, means forperforming an input/output data transfer operation comprising: a controlregister having a plurality of bit positions, control means connected tosaid control register to be responsive to the microinstructionscontained in said control register for performing the logical operationsspecified by the microinstructions instructions in said controlregister, a microinstruction loop, comprising first and secondmicroinstructions, contained in said storage unit, said control meansincluding: a. storage access means responsive to a first plurality ofpredetermined bit positions in said first microinstruction for readingthe character at a predetermined address in said storage unit, b. acomparison means, connected to said storage unit, responsive to saidfirst microinstruction, for comparing the characters read from saidstorage unit to a bit pattern representing a predetermined set ofcharacters and developing an output signal representing the occurrenceof a character of said predetermined set, c. incrementing meansoperative to increment the predetermined address for deriving thelocation of the next character to be addressed, d. means for generatinga share cycle signal indicating that a transfer of data between thecentral processing unit and an input/output device has been effected, e.means responsive to said first microinstruction and to the absence ofsaid share cycle signal for inhibiting the operation of said addressincrementing means, and means responsive to said second microinstructionto branch back to said first microinstruction.
 14. The combinationaccording to claim 13 further including means responsive to said outputsignal for terminating said data transfer operation.
 15. The combinationaccording to claim 13 further including means responsive to said outputsignal for modifying the data to be transferred.